1. Field of the Invention
The present invention relates to a semiconductor device having an insulation film whose breakdown voltage is improved and its manufacturing method, and more particularly to a gate insulation film of a MOS transistor, a dielectric layer of a capacitor, and an inter-insulation film formed between a floating gate and a control gate in a cell transistor of a nonvolatile memory such as an EPROM, and their suitable manufacturing method.
2. Description of the Related Art
Generally, a thermal oxide film, which is formed by thermally oxidizing a surface of a silicon substrate, has been used as a gate insulation film of a MOS transistor. However, in a case where the thermal oxide film is used as a gate insulation film, BMD (Bulk Micro Defect) due to oxygen contained in silicon of the silicon substrate is introduced into the gate insulation film in forming the thermal oxide film by thermally oxidizing the surface of the silicon substrate. As a result, insulation breakdown voltage defect of B mode caused by BMD accounts for about 30% of the manufactured device, so that yield of the manufacture is reduced. The breakdown voltage defect of the gate insulation film caused by BMD accounts for 5 to 7% of the defectiveness of the manufacture.
In J. Electrochem, Soc,: SOLID-STATE SCIENCE AND TECHNOLOGY May 1972, Vol. 119, No. 5, pp. 597-603, C. M. Osburn and D. W. Ormond "Dielectric Breakdown in Silicon Dioxide films on Silicon", an electrostatic breakdown of a thermal oxide film formed on silicon is specifically described.
Also, in for example, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-31, NO. 12, DECEMBER 1984, pp. 1736-2741 Fu-tai Liou and Shih-ou Chen "Evidence of Hole Flow in Silicon Nitride for Positive Gate Voltage", there are disclosed a MOS transistor having a gate insulation film having an ONO structure in which a bottom oxide film, a silicon nitride film, and a top oxide film are stacked, and a MOS capacitor having a dielectric layer having an ONO structure.
In a cell transistor (EPROM cell) of a nonvolatile memory such as an EPROM, there has been known a structure using the ONO structure as an inter-insulation film formed between a control gate and a floating gate similar to the gate insulating film of the MOS transistor described in the latter document.
For example, the EPROM cell having the inter-insulation film of the ONO structure is formed as follows.
First of all, a surface of a P type silicon substrate is selectively thermally oxidized so as to form a field oxide film by LOCOS. The surface of the substrate of a device area surrounded with the field oxide film is thermally oxidized so as to form a first thermal oxide film having a thickness of about 200 .ANG.. Then a first polysilicon layer having a thickness of about 1000 .ANG. is formed on the first thermal oxide film. Phosphorus is doped to the first polysilicon layer by thermal diffusion. Thereafter, the polysilicon is selectively etched Sequentially, thermal oxidization is performed at temperature of 950 to 1000.degree. C., so that a second thermal oxide film having a thickness of about 60 .ANG. is formed on the surface of the first polysilicon layer. Then, a silicon nitride layer (Si.sub.3 N.sub.4 film) having a thickness of about 150 .ANG. is deposited thereon by low-pressure CVD method, and thermal oxidation is performed again at temperature of about 1000.degree. C., so that a third thermal oxide film having a thickness of about 60 .ANG. is formed on the surface. A second polysilicon layer is deposited on the resultant structure, and phosphorus is doped thereto by thermal diffusion.
Thereafter, the second polysilicon layer, the third thermal oxide film, the Si.sub.3 N.sub.4 film, the second thermal oxide film, the first polysilicon layer, and the first thermal oxide film are sequentially etched by photoetching. As a result, there is formed a stacked gate structure in which a control gate, a second gate insulation film (SiO.sub.2 film/Si.sub.3 N.sub.4 film/SiO.sub.2 film), a floating gate, and a first gate insulation film are sequentially stacked.
Next, the above stacked gate structure is used as a mask, and N type impurities are ion-implanted to the silicon substrate, and thermal treatment is provided thereto, so that an N.sup.+ drain region and a N.sup.+ source region formed. Also, an oxide film is formed on an upper surface of the stacked gate structure and a side wall portion, and an exposed surface of the silicon substrate.
Thereafter, an inter-level insulation film (e.g., PSG film) is deposited on the resultant structure and selectively etched, so that a contact hole is formed on the drain region and the source region. Then, Al-Si-Cu film is formed on the entire surface of the inter-level insulation film and patterned. As a result, a drain electrode and a source electrode are formed, and an EPROM cell is formed.
The above-mentioned EPROM cell is a device in which a positive high voltage is applied to the N+ drain region and the control gate and electrons are injected to the floating gate, thereby writing is performed. The injected electrons are needed to be stored in the floating gate for a long period of time.
However, in the above-mentioned the manufacturing method of the EPROM cell, the bottom oxide film is formed by oxidizing the surface of the polysilicon layer to which impurities are doped. The formed bottom oxide film becomes weak by influence of dopant (phosphorus) and that of grain of polysilicon. The top oxide film is formed by thermally oxidizing the surface of Si.sub.3 N.sub.4 film. However, if dust is present on the surface of the Si.sub.3 N.sub.4 film, the portion where dust present is first oxidized. Due to this, a pin hole is generated on the top oxide film, and insulation breakdown voltage is reduced. For the above reason, the voltage of the inter-insulation film of the ONO structure is reduced, the electrons stored in the floating gate are absorbed by the control gate through the bottom oxide film, the Si.sub.3 N.sub.4 film, and the top oxide film, so that there is possibility that stored data will be erased. The emission of the electrons stored in the floating gate is a fatal defectiveness in the EPROM cell even if the frequency of the generation is rare.
As mentioned above, in the conventional semiconductor device having the insulation film formed by thermally oxidizing the surface of the silicon substrate, there was a problem in which the breakdown voltage of the insulation film is reduced by the influence of the substrate BMD. Also, in the conventional semiconductor device having the insulation film formed by thermally oxidizing the polysilicon layer or the surface of the SiN film, there was a problem in which the breakdown voltage of the insulation film is reduced by the influence of dopant, that of the grain of polysilicon, and presence of dust.